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MC14543B BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals
The MC14543B BCD-to-seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is constructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4-bit storage latch and an 8421 BCD-to-seven segment decoder and driver. The device has the capability to invert the logic levels of the output combination. The phase (Ph), blanking (BI), and latch disable (LD) inputs are used to reverse the truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to the Ph input of the circuit and the electrically common backplane of the display. The outputs of the circuit are connected directly to the segments of the LC readout. For other types of readouts, such as light-emitting diode (LED), incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet. Applications include instrument (e.g., counter, DVM etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses.
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16 PDIP-16 P SUFFIX CASE 648 MC14543BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MC14543B AWLYWW 14543B AWLYWW
* * * * * * * *
Latch Storage of Code Blanking Input Readout Blanking on All Illegal Input Combinations Direct LED (Common Anode or Cathode) Driving Capability Supply Voltage Range = 3.0 V to 18 V Capable of Driving 2 Low-power TTL Loads, 1 Low-power Schottky TTL Load or 2 HTL Loads Over the Rated Temperature Range Pin-for-Pin Replacement for CD4056A (with Pin 7 Tied to VSS). Chip Complexity: 207 FETs or 52 Equivalent Gates
ORDERING INFORMATION
Device MC14543BCP Package PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin Iin PD TA Tstg IOHmax IOLmax POHmax POLmax Parameter DC Supply Voltage Range Input Voltage Range, All Inputs DC Input Current per Pin Power Dissipation, per Package (Note 3.) Operating Temperature Range Storage Temperature Range Maximum Continuous Output Drive Current (Source or Sink) Maximum Continuous Output Power (Source or Sink) (4.) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 10 (per Output) 70 (per Output) Unit V V mA mW C C mA mW
MC14543BD MC14543BDR2 MC14543BF MC14543BFEL
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C 4. POHmax = IOH (VOH - VDD) and POLmax = IOL (VOL - VSS)
(c) Semiconductor Components Industries, LLC, 2000
v
v
1
March, 2000 - Rev. 3
Publication Order Number: MC14543B/D
MC14543B
PIN ASSIGNMENT
LD C B D A PH BI VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD f g e d c b a
TRUTH TABLE
Inputs LD X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 BI Ph* 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X C X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X XX0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 Outputs BAabcde 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 ** Inverse of Output Combinations Above 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 f 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 g 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Display Blank 0 1 2 3 4 5 6 7 8 9 Blank Blank Blank Blank Blank Blank ** Display as above
XX
X = Don't care = Above Combinations * = For liquid crystal readouts, apply a square wave to Ph For common cathode LED readouts, select Ph = 0 For common anode LED readouts, select Ph = 1 ** = Depends upon the BCD code previously applied when LD = 1
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MC14543B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 10 15 IOL 5.0 10 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 -- - 1.6 - 4.2 0.64 1.6 -- 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 -- - 1.3 - 3.4 0.51 1.3 -- 3.4 -- -- -- -- -- - 4.2 - 0.88 - 10.1 - 2.25 - 8.8 0.88 2.25 10.1 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 -- - 0.9 - 2.4 0.36 0.9 -- 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Characteristic Symbol VOL Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (5.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 0.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 9.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 A Total Supply Current (6.) (7.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.6 A/kHz) f + IDD IT = (3.1 A/kHz) f + IDD IT = (4.7 A/kHz) f + IDD Adc 5. Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10-3 (CL - 50) VDDf where: IT is in A (per package), CL in pF, VDD in V, and f in kHz is input frequency. 7. The formulas given are for the typical characteristics only at 25_C.
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MC14543B
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SWITCHING CHARACTERISTICS (8.) (CL = 50 pF, TA = 25_C)
Characteristic Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Symbol VDD 5.0 10 15 5.0 10 15 tPLH 5.0 10 15 tPHL 5.0 10 15 tsu 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- 350 450 500 40 30 20 250 100 80 125 50 40 505 205 155 1650 660 495 -- -- -- -- -- -- -- -- -- ns -- -- -- 605 250 185 1210 500 370 ns Min -- -- -- -- -- -- Typ 100 50 40 100 50 40 Max 200 100 80 200 100 80 ns Unit ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 12.5 ns Turn-Off Delay Time tPLH = (1.7 ns/pF) CL + 520 ns tPLH = (0.66 ns/pF) CL + 217 ns tPLH = (0.5 ns/pF) CL + 160 ns Turn-On Delay Time tPHL = (1.7 ns/pF) CL + 420 ns tPHL = (0.66 ns/pF) CL + 172 ns tPHL = (0.5 ns/pF) CL + 130 ns Setup Time tTHL ns Hold Time th ns Latch Disable Pulse Width (Strobing Data) tWH ns 8. The formulas given are for the typical characteristics only.
LOGIC DIAGRAM
BI 7 VDD = PIN 16 VSS = PIN 8
A5
9a 10 b
B3
11 c 12 d
C2
13 e 15 f
D4
14 g
LD 1
PHASE 6
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MC14543B
0 IOH, SOURCE CURRENT (mAdc) POHmax = 70 mWdc VDD = 5.0 Vdc IOL , SINK CURRENT (mAdc) 18 24 VDD = 15 Vdc
- 6.0
- 12
VDD = 10 Vdc
12
VDD = 10 Vdc
- 18 VDD = 15 Vdc - 24 - 16 VSS = 0 Vdc - 12 - 8.0 - 4.0 (VOH - VDD), SOURCE DEVICE VOLTAGE (Vdc) 0
6.0 VDD = 5.0 Vdc 0 0 POLmax = 70 mWdc VSS = 0 Vdc 4.0 8.0 12 (VOL - VSS), SINK DEVICE VOLTAGE (Vdc) 16
Figure 1. Typical Output Source Characteristics
Figure 2. Typical Output Sink Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high. 20 ns C tPHL 90% g 50% tTHL 90% 10% 20 ns 50% tPLH 10% tTLH VDD VSS VOH VOL
(b) Inputs D, Ph, and BI low, and Inputs A and B high. 20 ns LD Inputs BI and Ph low, and Inputs D and LD high. f in respect to a system clock. All outputs connected to respective CL loads. 20 ns A, B, AND C 10% 20 ns 90% 50% 1 2f 50% DUTY CYCLE VDD VSS (c) Data DCBA strobed into latches VOH VOL VDD LD 50% tWH VSS g tsu C 50% 90% 10% 50% VSS th 50% VDD VSS VOH VOL VDD
ANY OUTPUT
Figure 3. Dynamic Power Dissipation Signal Waveforms
Figure 4. Dynamic Signal Waveforms
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MC14543B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIQUID CRYSTAL (LC) READOUT
MC14543B OUTPUT Ph ONE OF SEVEN SEGMENTS COMMON BACKPLANE MC14543B OUTPUT Ph
INCANDESCENT READOUT
APPROPRIATE VOLTAGE
SQUARE WAVE (VSS TO VDD)
VSS
LIGHT EMITTING DIODE (LED) READOUT
VDD
GAS DISCHARGE READOUT
APPROPRIATE VOLTAGE
COMMON CATHODE LED MC14543B OUTPUT Ph
COMMON ANODE LED
MC14543B OUTPUT Ph VDD
VSS
MC14543B OUTPUT Ph
NOTE: Bipolar transistors may be added for gain (for VDD
v 10 V or Iout 10 mA).
VSS
CONNECTIONS TO SEGMENTS
a f e d VDD = PIN 16 VSS = PIN 8 g b c
DISPLAY
0
1
2
3
4
5
6
7
8
9
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MC14543B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14543B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC14543B/D

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